The present invention relates to a semiconductor memory device fabricated on a semiconductor substrate.
As a memory device having a large memory capacity, a semiconductor memory device employing dynamic memory cells has been widely utilized. One example of such type of semiconductor memory device is disclosed in detail in U.S. Pat. No. 4,031,522. In such a memory device, e.g., a memory cell, the so-called "single transistor type of cell" consisting of one transfer gate transistor and one capacitor is used. Each pair of two adjacent data lines extending in the column direction are adapted to be coupled to two inputs of corresponding one of differential type sense amplifiers arrayed in a row direction. In a memory device having the aforementioned construction, upon reading, the electric charge which has been already stored in the capacitor of the memory cell depending upon the information written into the memory cell is necessarily divided between the capacitance of the memory cell capacitor and the capacitance of the data line, and hence, the resultant voltage, that is, the voltage on the data line produced by the divided electric charge must be detected by the sense amplifier.
In general, a size of memory cells and especially a size of capacitors in the memory cells tends to be reduced as a memory capacity is successively increased to 64K bits, 256K bits, 1M bits and so on. This implies reduction of the electric charge stored in a capacitor of a memory cell, and results in an extremely small read signal. On the other hand, since a sense amplifier is provided for each corresponding pair of two adjacent data lines, the reduction of the size of the memory cells naturally results in reduction of the pitch of the array of the data lines, and accordingly the sense amplifiers are also compelled to reduce their respective pitch, i.e., the width in the row direction, to the extent corresponding to the reduction in size of the memory cells. Hence, realization of a high sensitivity of sense amplifier has been greatly prohibited. In other words, this means that if sense amplifiers having a high sensitivity require on a relatively large chip area, then a high density integration of a large capacity memory cannot be achieved.
Further, since the width of an area assigned for a sense amplifier is limited within the interval of paired data lines, the length of the area inevitably becomes very large. This makes the area a very lengthy rectangular shape which is unfavorable for effective realization of the sense amplifier.
For this reason, as memory capacities have been successively increased, it has become very difficult to accommodate the aforementioned sense amplifier in one pitch of the memory cell array, and this was one of the obstacles against realization of a high density memory device in the prior art. Furthermore, in accordance with the reduction in size of memory cells, enhancement of a sensitivity of a sense amplifier has been required, but it has also been difficult with present circuit technique to realize highly sensitive sense amplifiers under a limited pitch condition of the array.